1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a memory device wherein a group of multiple memory cells is divided into a plurality of memory cell blocks, and the output of each memory cell block is connected to a main data line.
2. Description of the Prior Art
The conventional large-capacity static RAMs having, for example, a capacity of 256 kilobits are mostly composed of 512 rows and 512 columns. However, due to the necessity of shortening the bit lines to achieve a higher speed, there is noted a recent trend toward increasing the number of columns such as, for example, to 256 rows and 1024 columns. As a result of such numerical increase of columns, the number of memory cells selectable by a single word line is also increased to consequently bring about an increase of the current consumption. In order to solve this problem, there has been appearing another new trend toward reducing the number of memory cells selectable by a single word line.
FIG. 4 is a layout diagram showing such an exemplary static RAM 1a. Denoted by 2 is a memory cell group which consists of memory cells arrayed to form 256 rows and 1024 columns. The memory cell group 2 is divided into a plurality of memory cell blocks 2.sub.1 -2.sub.8 (8 blocks in this example, but the number may be 16 or 4 without being limited to 8 alone), and each of such memory cell blocks 2.sub.1 -2.sub.8 consists of memory cells in an array of 256 rows and 128 columns so that 128 memory cells are selectable by a single word line.
Sense amp blocks SA1, SA2, . . . . SA8 are disposed adjacent to the memory cell blocks 2.sub.1, 2.sub.2, . . . . 2.sub.8, and the data read out from the memory cell via a pair of bit lines is fed to a local data line via a MOS FET controlled by a column select signal. The signal thus obtained from the local data line is amplified by the sense amp blocks SA1, SA2, . . . . SA8. Denoted by BS1, BS2, . . . . BS8 are block select blocks which are disposed adjacent to the sense amp blocks SA1, SA2, . . . . SA8 and serve to pass the output signal of the sense amp block SA therethrough in response to a block select signal. The entire output terminals of the block select blocks BS1, BS2, . . . . BS8 are connected to a main data line 4.
There are also shown a data hold circuit 5a for holding the data signal transferred thereto via the main data line 4, an output buffer circuit 6, and an output terminal 7.
FIG. 5 is a specific circuit diagram of a conventional exemplary memory device having the layout of FIG. 4.
There is shown in FIG. 5 a memory cell 8 connected to a power supply terminal (+Vcc) via MOS FETs M1, M2; a pair of bit lines B, B connected to the memory cell 8 and also to the terminal (+Vcc) in the same manner; and an equalizing MOS FET M3 connected between a pair of bit lines B, B and serving to short-circuit the bit lines B, B in response to an equalizing signal .phi.E.
A pair of local data lines 9, 9 are connected to the bit lines B, B via MOS FETs M4, M5. In response to a column select signal, the MOS FETs M4, M5 serve to connect the local data lines the bit lines B, B. A MOS FET M6 functions to equalize between the local data lines 9, 9 and is controlled by an equalizing signal .phi.E in the same manner as the MOS FET M3. The signal read out via the local data lines 9, 9 amplified by the sense amp block SA. The sense amp block SA consists of three differential amplifiers A1, A2, A3 and an equalizing MOS FET M7. The output signal of the sense amp block SA is transferred via the block select block BS to the main data line 4. The block select block BS comprises a switch circuit consisting of a parallel connection of an N-channel MOS FET M8 and a P-channel MOS FET M9, a NAND circuit NA1 supplied with an equalizing signal .phi.E and a block select signal BS, and an inverter 11 for inverting the output signal of the NAND circuit NA1. The above switch circuit is held in its on-state except for the period of equalization with the block selection being effected.
An output buffer control circuit 5a comprises a NOR circuit NR1, a NAND circuit NA2 and inverters I2, I3, I4. The data signal from the main data line 4 is fed to one input terminal of the NOR circuit NR1 while an output-disable signal OD is fed to the other terminal thereof, and an output signal of the NOR circuit NR1 is transferred to the inverter I3. The data signal from the main data line 4 is fed also to one input terminal of the NAND circuit NA2 while a signal obtained by inverting the output disable signal OD through the inverter I2 is fed to the other input terminal thereof, and the output signal of the NAND circuit NA2 is transferred to the inverter I4.
An output buffer circuit 6 comprises a P-channel MOS FET M10 and an N-channel MOS FET M11. The output signal of the inverter I3 is fed to the gate of the MOS FET M10 while the output signal of the inverter I4 is fed to the gate of the MOS FET M11, and the junction of the MOS FETs M10 and M11 is connected to the output terminal 7.
In the memory device of the arrangement of FIG. 4, the bit lines can be shortened with reduction of the number of memory cells selectable by a single word line. However, since the main data line 4 is rendered correspondingly longer, it has been difficult to attain a sufficiently high speed by using this technique.
In view of the above problem, an improved technique has been contrived with additional provision of a precharge circuit. This precharge circuit is driven by a pulse (equalizing signal) produced on the basis of the output signal of an ATD (address transition detector), whereby the main data line is precharged to a half potential of the supply voltage Vcc FIG. 6 (A) shows an example of such precharge circuit, and FIG. 6 (B) is a timing chart thereof. There are shown an inverter I5 for inverting the data signal read out from the memory cell and amplified by the sense amplifier, and a switch circuit SW1 controlled by a pulse .phi.1 and serving to short-circuit the input and output of the inverter I5. The inverter I5 has a CMOS configuration comprising a P-channel MOS FET and an N-channel MOS FET, and is so designed as to generate a half output voltage of the supply voltage Vcc when its input and output are short-circuited by the switch circuit SW1. The output signal from the inverter I5 is transferred to a latch circuit 10 via a switch circuit SW2.
In the operation of the precharge circuit, both pulses .phi.1 and .phi.2 rise simultaneously, to turn on the switch circuit SW1, thereby short-circuiting the input and output of the inverter I5 while turning on the switch circuit SW2, to electrically connect the main data line 4 to the output terminal of the inverter I5. Accordingly, the main data line 4 is precharged to a half potential of the supply voltage Vcc by the action of the inverter I5. And after the lapse of a predetermined time required for the precharge, the pulse .phi.1 falls, to turn off the switch circuit SW1, and then the latch pulse LP rises. However, the pulse .phi.2 still remains high, and the data signal is latched by the latch circuit 10 in the state where the pulse .phi.1 is "low", the pulse .phi.2 is "high" and the latch pulse LP is "high".
Since the main data line is thus precharged by the precharge circuit, transition of the data signal on the data line can be expedited to consequently increase the read speed.
Meanwhile in the conventional example of FIG. 5, where the main data line 4 is not precharged, it is impossible to eliminate the limit that exists in enhancing the rapidity due to the lengthened main data line 4 as mentioned previously.
The desired rapidity can be attained by adding the precharge circuit shown in FIG. 6. However, because of the precharge circuit configuration where the inverter I5, the switch circuit SW2 and the latch circuit 10 are inserted in the data signal transmission path, it follows that the data signal is transmitted to the output side via the inverter I5, the switch circuit SW2 and the latch circuit 10. Consequently there occurs a transmission delay of the data signal as a natural result. Therefore, even though the rapidity can be enhanced by such precharge, the delay caused by the signal passage through the inverter I5 and the switch circuit 10 needs to be subtracted, so that the rapidity fails to be effectively improved.
In addition, due to the necessity of producing particular pulses such as pulses .phi.1, .phi.2 and the latch pulse LP, circuits for generation of such pulses are required in particular to consequently render the circuit configuration more complicated.